Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design

PROCESS VARIATIONS IN SEMICONDUCTOR manufacturing and their potentially negative impact on VLSI designs are well-known phenomena. Papers published in IEEE transactions and conference proceedings date back to the 1970s. Traditionally, variability has been considered a manufacturing problem in which the device and process engineers were supposed to minimize the variations. To guardband the impact of the residue variability, the designers were usually given a set of ‘‘corner’’ models in which the bestand worst-case models were specified. As CMOS technology is scaled down into the nanometer range, variation control becomes much more challenging, having a fundamental impact on all aspects of IC design. Although continual improvements in manufacturing processes mitigate some of variability’s negative effects, the semiconductor industry is starting to accept that certain effects are better mitigated during the design phase. Handling variability in the design step will require accurate, consistent models of variability and its dependence on designable parameters, and of variability’s spatial and temporal distributions. Such models are quite different from the corner models deployed thus far to model manufacturing variability. Consequently, the compact modeling of systematic, spatial, and random variations is essential to abstract the physical-level variations into a format that designers can use. With the support of the IEEE Electron Device Society, the ACM Special Interest Group in Design Automation, and the Semiconductor Research Corporation (SRC), we organized the first Compact Variability Modeling Workshop in 2008. The workshop’s goal was to bring together industry and academic experts with wide knowledge of device engineering, compact modeling, circuit design, and VLSI CAD so that they could address the challenges of variability. This special issue of IEEE Design & Test highlights, and expands upon, some of the presentations given at that workshop. Process variations usually manifest as parameter fluctuations in a CMOS transistor. They are induced by the limits of either fundamental physics, such as random dopant fluctuations and line-edge roughness, or by the manufacturing process, such as the variability associated with gate dielectrics. As the minimum feature size is scaled toward 10 nm, both the amount of process variations and the sensitivity of circuit performance to variations are escalating. The first article in this issue, ‘‘Modeling Process Variability in Scaled CMOS Technology’’ by Samar Saha, reviews the predominant contributors of variations in sub-90-nm CMOS transistors. The article presents an overview of different modeling approaches (e.g., statistical corner model) that transfer the variability from the process domain into circuit simulation and the VLSI design environment. At recent technology nodes, a major process variation is layout-dependent fluctuation from advanced manufacturing process techniques. The variations can result from sub-wavelength lithography, strained silicon engineering, and ion implantation, for example. These techniques enhance a CMOS transistor’s Compact Variability Modeling for Nanometer CMOS Technology